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Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
SDA/SDAIN
t BUF
t LOW
t SU, DAT
t HD, DAT
t SU, STA
t HD, STA
t SU, STO
SCL
t HIGH
t HD, STA
START CONDITION
t R
t F
REPEATED START CONDITION
STOP
START
Figure 5. Serial Interface Timing Details
Table 3. Programmable Device Address Settings
DEVICE ADDRES S
CONDITION
CONDITION
B7
0
B6
1
B5
0
B4
A3
B3
A2
B2
A1
B1
A0
Device Address (AD0)
The MAX5980 is programmable to 1 of 16 unique slave
device addresses. The three MSBs of the device address
are always [010]. The 4 LSBs of the device address are
programmable, and are formed by the states of the Slave
Address Inputs (A0, A1, A2, and A3; see Table 3). To
program the device address, connect A0, A1, A2, and
A3 to a combination of V DD (logical 1) and DGND (logi-
cal 0), and initiate a device reset.
I 2 C-Compatible Serial Interface
The device operates as a slave that sends and receives
data through an I 2 C-compatible, 2-wire or 3-wire inter-
face. The interface uses a serial-data input line (SDAIN),
a serial-data output line (SDAOUT), and a serial-clock line
(SCL) to achieve bidirectional communication between
master(s) and slave(s). A master (typically a microcon-
troller) initiates all data transfers to and from the device,
and generates the SCL clock that synchronizes the data
22
transfer. In most applications, connect the SDAIN and
the SDAOUT lines together to form the serial-data line
(SDA). Most of the figures shown label the bus as SDA.
Using the separate input and output data lines allows
optocoupling with the controller bus when an isolated
supply powers the microcontroller.
The device's SDAIN line operates as an input and
SDAOUT operates as an open-drain output. A pullup
resistor, typically 4.7k I , is required on SDAOUT (3-wire
mode) or SDA (2-wire mode). The SCL line operates only
as an input. A pullup resistor, typically 4.7k I , is required
on SCL if there are multiple masters, or if the master in
a single-master system has an open-drain SCL output.
Serial Addressing
Each transmission consists of a START condition sent by
a master, followed by the device's 7-bit slave address
plus R/W bit, a register address byte, 1 or more data
bytes, and finally a STOP condition.
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